LCD devices are known in the art. See, for example, U.S. Pat. Nos. 7,602,360; 7,408,606; 6,356,335; 6,016,178; and 5,598,285, each of which is hereby incorporated herein in its entirety.
FIG. 1 is a cross-sectional view of a typical LCD display device 1. The display device 1 generally includes a layer of liquid crystal material 2 sandwiched between first and second substrates 4 and 6, and the first and second substrates 4 and 6 typically are borosilicate glass substrates. The first substrate 4 often is referred to as the color filter substrate, and the second substrate 6 often is referred to as the active or TFT substrate.
The first or color filter substrate 4 typically has a black matrix 8 formed thereon, e.g., for enhancing the color quality of the display. To form the black matrix, a polymer, acrylic, polyimide, metal, or other suitable base may be disposed as a blanket layer and subsequently patterned using photolithography or the like. Individual color filters 10 are disposed in the holes formed in the black matrix. Typically, the individual color filters often comprise red 10a, green 10b, and blue 10c color filters, although other colors may be used in place of or in addition to such elements. The individual color filters may be formed photolithographically, by inkjet technology, or by other suitable technique. A common electrode 12, typically formed from indium tin oxide (ITO) or other suitable conductive material, is formed across substantially the entirety of the substrate or over the black matrix 12 and the individual color filters 10a, 10b, and 10c. 
The second or TFT substrate 6 has an array of TFTs 14 formed thereon. These TFTs are selectively actuatable by drive electronics (not shown) to control the functioning of the liquid crystal light valves in the layer of liquid crystal material 2. TFT substrates and the TFT arrays formed thereon are described, for example, in U.S. Pat. Nos. 7,589,799; 7,071,036; 6,884,569; 6,580,093; 6,362,028; 5,926,702; and 5,838,037, each of which is hereby incorporated herein in its entirety.
Although not shown in FIG. 1, a light source, one or more polarizers, alignment layers, and/or the like may be included in a typical LCD display device.
Conventional TFT arrays for LCD TVs, monitors, notebook displays, cell phone displays, etc., often are fabricated by first depositing and patterning a gate material and then depositing and patterning, sequentially, the gate insulator, amorphous silicon layer, source/drain metal, passivation layer, and pixel electrode. The manufacturing process involves three physical vapor deposition (PVD) or sputtering steps for the conductors, and several plasma-enhanced combustion vapor deposition (PECVD) steps at an elevated temperature (e.g., at a temperature of at least about 300-350 degrees C.) for the gate insulator, semiconductor, and passivation layers. These deposition processes are interrupted by photolithographic steps for patterning the layers.
It will be appreciated that this current manufacturing flow involves a number of processes, materials, techniques, etc., that often are interrupted by a number of further sub-process steps. In addition, the high temperatures involved in current techniques restrict the types of materials that can be used as the substrates.
Thus, it will be appreciated that there is a need in the art for a simple, low-temperature manufacturing flow for forming a TFT substrate for use in display devices and/or the like.
One aspect of certain example embodiments relates to techniques for providing a simple, low-temperature manufacturing flow for forming a TFT substrate for use in display devices for fabricating the semiconductor, gate insulator, and gate metal layers sequentially as blanket layers.
Another aspect of certain example embodiments relates to disposing blanket layers for the TFT array prior to any patterning steps on the TFT substrate.
Another aspect of certain example embodiments relates to the use of high-throughput, large area coaters. Such equipment may be found, for example, in glass production plants, and may allow for better economies of scale to be achieved.
Certain example embodiments of this invention relate to a method of making a TFT substrate for an electronic device. A glass substrate is provided. An oxide semiconductor blanket layer is sputter deposited, at low or room temperature, directly or indirectly, on the glass substrate. A gate insulator blanket layer is deposited, directly or indirectly, on the oxide semiconductor blanket layer. A gate metal blanket layer is deposited, directly or indirectly, on the gate insulator blanket layer. A mask is applied over one or more portions of the gate metal blanket layer so as to define one or more corresponding masked areas and one or more corresponding unmasked areas. Portions of the gate metal blanket layer and portions of the gate insulator blanket layer are removed at or proximate to the one or more unmasked areas. Conductivity of the oxide semiconductor layer is increased at or proximate to the one or more unmasked areas. A passivation layer is disposed across substantially the entire substrate. The passivation layer is patterned so as to define source and drain contact holes. A layer for source and drain connections is deposited.
Some or all of the above-described steps may be performed at a first location and some or all of the remaining steps may be performed at a second or different location (e.g., after the layer has been shipped to a fabricator, LD manufacturer, etc.). For instance, a first party may perform barrier, oxide semiconductor, gate insulator, and/or gate metal layer depositions, and a second party (e.g., at a second location) may perform patterning, activation, pixel electrode deposition, and/or other steps.
Certain example embodiments of this invention relate to a method of making a TFT substrate for an electronic device. A soda lime glass substrate is provided. An oxide semiconductor layer is sputter deposited, at low or room temperature, directly or indirectly, on substantially an entire major surface of the glass substrate. A gate insulator layer is deposited on substantially the entire major surface of the glass substrate over at least portions of the oxide semiconductor layer. A gate metal layer is deposited, directly or indirectly, on at least portions of the gate insulator layer. The oxide semiconductor layer is patterned prior to deposition of the gate metal layer. Conductivity of portions of the oxide semiconductor layer is increased. A passivation layer is disposed across substantially the entire substrate. The passivation layer is patterned so as to define source and drain contact holes. A layer for source and drain connections is deposited. In certain example embodiments, the patterning of the oxide semiconductor layer is performed prior to deposition of the gate insulator layer. In certain example embodiments, the oxide semiconductor layer and the gate insulator layer are patterned together or at the same or substantially the same time (e.g., in the same step).
A method of making an electronic display device may comprise making a TFT substrate according to this method or a variant thereof. For instance, in the case of an LCD, a color filter substrate may be provided, and a layer of liquid crystal material may be disposed between the color filter substrate and the TFT substrate.
Certain example embodiments of this invention relate to an electronic device including a TFT substrate. The TFT substrate comprises a soda lime glass substrate (e.g., as opposed to a borosilicate glass substrate, which may be used in different embodiments of this invention). A silicon-inclusive barrier layer is sputter deposited at low or room temperature, directly or indirectly, on the soda lime glass substrate (e.g., to help reduce and sometimes even eliminate the migration of sodium from the glass substrate into one or more of the thin film and/or other layers on the substrate). An oxide semiconductor layer comprising IGZO, amorphous or polycrystalline ZnO, ZnSnO, or InZnO, is sputter deposited at low or room temperature, directly or indirectly, on the barrier layer. A gate insulator layer is sputter deposited at low or room temperature, directly or indirectly, on the oxide semiconductor layer. A gate metal layer is sputter deposited at low or room temperature, directly or indirectly, on the gate insulator layer. One or more portions of the gate insulator layer and the gate metal layer are removed to expose the underlying oxide semiconductor layer. One or more portions of the oxide semiconductor layer are removed to create at least one island, the at least one island being plasma treated so as to increase the conductivity thereof. A passivation layer is deposited atop the barrier layer, the at least one island, and the gate insulator layer, the passivation layer being patterned to form source and drain contact holes. Source and drain lines are deposited over at least a portion of the passivation layer and in the source and drain contact holes.
The features, aspects, advantages, and example embodiments described herein may be combined to realize yet further embodiments.